Leilei Jin

Leilei Jin

Ph.D., Postdoctoral Researcher
Department of Computer Science and Engineering
The Chinese University of Hong Kong
Office: Rm 905, Ho Sin Hang Engineering Building
Email: leileijin@cuhk.edu.hk
Google Scholar ORCID

Biography

I am a Postdoctoral Researcher at the Department of Computer Science and Engineering, The Chinese University of Hong Kong (CUHK), working with Prof. Tsung-Yi Ho since 2025. Previously, I received my Ph.D. from Southeast University (SEU) in 2024.

My research focuses on Electronic Design Automation (EDA) for advanced technology nodes, with an emphasis on the 3D IC — BSPDN — DTCO co-design methodology. I develop physical design automation techniques for 3D integrated circuits, back-side power delivery networks (BSPDN), and design-technology co-optimization (DTCO) to address the interconnect, power, and thermal challenges in next-generation chip design.

Education

Research Interests

Advanced Technology Nodes 3D IC BSPDN DTCO Physical Design Automation

Publications

2026
C19 Haoyang Xu, Zheng Yang, Zhen Zhuang, Leilei Jin, Bei Yu, Sung Kyu Lim, Tsung-Yi Ho, RTL-3D: Timing-aware Tier Partitioning for 3D ICs Using Pre-synthesis Timing Analysis,
ACM/IEEE Design Automation Conference (DAC), Long Beach, Jul. 26–29, 2026
C18 Shanyi Li, Leilei Jin, Siyuan Liang, Zhen Zhuang, Rongmei Chen, Bei Yu, Tsung-Yi Ho, FlexiCTS: CPPR-Aware 3D Clock Tree Synthesis for Face-to-Face Bonded ICs,
ACM/IEEE Design Automation Conference (DAC), Long Beach, Jul. 26–29, 2026
C17 Leilei Jin, Haoyang Xu, Siyuan Liang, Zhen Zhuang, Zhou Hu, Zixiao Wang, Bei Yu, Rongmei Chen, Tsung-Yi Ho, BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs,
ACM/IEEE Design Automation Conference (DAC), Long Beach, Jul. 26–29, 2026
C16 Siyuan Liang, Shanyi Li, Leilei Jin, Yuan Pu, Yushen Zhang, Zhen Zhuang, Kai-Yuan Chao, Ulf Schlichtmann, Tsung-Yi Ho, BLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/Ground Plane Synthesis,
ACM/IEEE Design Automation Conference (DAC), Long Beach, Jul. 26–29, 2026
C15 Jiajie Xu, Leilei Jin, Ziyue Han, Yanlong Mao, Liangji Wu, Chenpu Shi, Yunfan Zuo, Lizheng Ren, Hao Yan, Xingquan Li, Longxing Shi, DiffDEG: Diffusion-Enhanced Design Evolution Graph Representation Learning for Post-Layout Optimization,
ACM/IEEE Design Automation Conference (DAC), Long Beach, Jul. 26–29, 2026
C14 Haoyang Xu, Zhen Zhuang, Leilei Jin, Zheng Yang, Chen Wu, Lei He, Sung Kyu Lim, Tsung-Yi Ho, Mixed-structure Double-sided Redistribution Layer Routing for Glass Interposer-based 5.5D ICs,
ACM/IEEE Design Automation Conference (DAC), Long Beach, Jul. 26–29, 2026
C13 Liang Xiao, Qinkai Duan, Leilei Jin, Jinwei Liu, Tsung-Yi Ho, Evangeline F.Y. Young, Martin Wong, TP-GR: An Efficient Global Router for Timing and Power Co-optimization, Best Paper
ACM International Symposium on Physical Design (ISPD), pp. 1-6, 2026
C12 Zixian Yang, Shanyi Li, Leilei Jin, Tsung-Yi Ho, Chien-Nan Jimmy Liu, IDDA-3D: Inter-Die Delay Aware Timing-Driven Placement on Face-to-Face bonded 3D ICs,
ACM International Symposium on Physical Design (ISPD), pp. 1-6, 2026
C11 Shuo Ren, Zhen Zhuang, Flynn, Leilei Jin, Libo Shen, Bei Yu, Tsung-Yi Ho, Partitioning-free 3D-IC Floorplanning,
Asia and South Pacific Design Automation Conference (ASPDAC), pp. 1-6, 2026
2025
C10 Leilei Jin, Rongliang Fu, Zhen Zhuang, Liang Xiao, Fangzhou Liu, Bei Yu, Tsung-Yi Ho, ChronoTE: Crosstalk-Aware Timing Estimation for Routing Optimization via Edge-Enhanced GNNs,
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1-9, 2025
2024
C9 Jiajie Xu, Ziyue Han, Leilei Jin, Shiyang Wu, Hao Yan, Longxing Shi, FACT: Fast and Accurate Multi-Corner Predictor for Timing Closure in Commercial EDA Flows,
ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD), pp. 1-7, 2024
C8 Junzhuo Zhou, Li Huang, Haoxuan Xia, Yihui Cai, Leilei Jin, Xiao Shi, Wei Xing, Ting-Jung Lin, Lei He, LVF2: A Statistical Timing Model Based on Gaussian Mixture for Yield Estimation and Speed Binning,
ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2024
C7 Jiajie Xu, Leilei Jin, Wenjie Fu, Longxing Shi, A Deep-Learning-Based Statistical Timing Prediction Method for Sub-16nm Technologies,
Design, Automation & Test in Europe Conference (DATE), pp. 1-6, 2024
2023
C6 Jiajie Xu, Leilei Jin, Hao Yan, An Accurate Statistical Cell Delay Model Considering Multiple-Input Switching Effect,
International Symposium of Electronics Design Automation (ISEDA), pp. 375-378, 2023
C5 Leilei Jin, Jiajie Xu, Wenjie Fu, Hao Yan, Xiao Shi, Ming Ling, Longxing Shi, A Novel Delay Calibration Method Considering Interaction Between Cells and Wires,
Design, Automation & Test in Europe Conference (DATE), pp. 1-6, 2023
2022
J3 Leilei Jin, Wenjie Fu, Hao Yan, Longxing Shi, A Statistical Cell Delay Model for Estimating the 3σ Delay by Matching Kurtosis,
IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 2932-2936, 2022
C4 Leilei Jin, Jiajie Xu, Wenjie Fu, Xiao Shi, A Quantile-Based SUM/MAX Operating Method for Statistical Timing Analysis,
IEEE International Conference on Solid-State & Integrated Circuit Technology (ICSICT), pp. 1-4, 2022
2021
J2 Leilei Jin, Wenjie Fu, Ming Ling, Longxing Shi, A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors with Spark Streaming,
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 353-364, 2021
2020
J1 Wenjie Fu, Leilei Jin, Ming Ling, Yu Zheng, Longxing Shi, VASTA: A Wide Voltage Statistical Timing Analysis Tool Based on Variation-Aware Cell Delay Models,
IEEE Access, vol. 8, pp. 197194-197202, 2020
C3 Wenjie Fu, Leilei Jin, Ming Ling, Yu Zheng, Longxing Shi, A Cross-Layer Power and Timing Evaluation Method for Wide Voltage Scaling,
ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2020
2019
C2 Wenjie Fu, Yu Zheng, Leilei Jin, Ming Ling, A Fast Reduction Method for Path Process Variations Without Time-Consuming Training,
IEEE International Conference on ASIC (ASICON), pp. 1-4, 2019
C1 Leilei Jin, Wenjie Fu, Yu Zheng, Hao Yan, A Precise Block-Based Statistical Timing Analysis with Max Approximation Using Multivariate Adaptive Regression Splines,
IEEE International Conference on ASIC (ASICON), pp. 1-4, 2019

Honors & Awards